The grouping signals further used to provide constraint value at different procedures. In this section, the signals which were defined in the first part is classified based in different group based on its type. It is the first section of SPF containing definition of all the signals with their type(In, Out, InOut etc) The SPF which is described in this article is based on stuck-at faults without compression. Let’s begin with the different segments categorized in SPF, described below:
Please check below SPF infrastructure segment for a more detailed structure of SPF. SPF is assigned at the run_drc stage to verify the compatibility of scan inserted netlist with the SPF, it further determines how the scan structure can be used to generate patterns and fault simulations. In general words, SPF portrays the information of scan structure, scan chain, initial state value for all the signals for particular test mode and furthermore.Īll the above-defined information in SPF is needed to guide the ATPG tool for DRC checks and pattern formatting. SPF stands for STIL(Standard test interface language) protocol file generated after the scan insertion stage, which consists of all the necessary and basic scan information. If the pattern simulation failure occurs, we need to analyze the failure and need to do necessary changes in ATPG stage like spf modification to clean up the simulation failures.If any Error or severe warnings occurs at ATPG/vector generation stage, it can either be solved at the same stage, else we need to jump to SCAN stage for the required changes which helps to clean ATPG issues.Once the design is ready with scan inserted netlist, test vectors will be generated and the same vectors will be used for simulation.Simulation/Pattern validation plays a vital role in DFT, in order to examine the vectors generated by the ATPG tool.Refer below figure to check the interdependency of all the stages. Simulation is the later stage after ATPG, for the validation of the patterns generated in different formats.Īll the stages are interdependent on each other. ATPG is performed on scan inserted design and the SPF generated through scan insertion.
Keywords: DFT (Design for testability), ATPG (Automatic test pattern generation), Simulation/Pattern validation, SPF (STIL protocol file).ĪTPG (Automatic test pattern generation) is the process of generating the test vectors for the particular test mode to check the manufacturing defects, which is further used by simulation tools for validation. In this article, we are going to understand how we can solve the gross simulation failure by understanding and editing the SPF skeleton at ATPG stage. Based on the matching responses of the circuit, goodness of chip will be defined, which in the end concludes the quality of the chip. Simulation’s pivotal role is to check if the binary response applied as an input that matches the values at the output response of the chip. By Namrata Makwana (eInfochips, an Arrow company)ĭesign For Testability(DFT) adds an extra Hardware/Structure in the existing functional design also called MBIST/Scan insertion to get controllability and observability of the design to make it easily testable after manufacturing i.e., post-silicon SOC testing.
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